KiCad is a great tool for taking your electronics design from schematic to PCB, but circuit simulation is secondary feature.
As we will see here KiCad does contain the ability to generate netlists which can be used with simulators like ngspice to perform circuit verification and analysis.
To get started we will need to decide on a design. I will choose a circuit which will show us how to do following:
Use vendor spice components
Perform Transient Analysis
Simulate an input signal
Measure frequency responce
Layout Circuit and Generate Netlist
For this demo let us pick a simple inverting op amp circuit. We can use the spice models from vendors like Texas Instruments and Linear Technology to provide the op amp. This also means we can easily, virtually, swap out components to see how they perform in our design.
Below we can see the completed schematic for a non-inverting op amp with a dual power supply. The 50K ohm feedback and 2K ohm input resistors mean our signal will be amplified 25 times. For more details on drawing schematics in kicad refer to the getting started tutorials.
Image 1: The completed inverting op amp schematic
Once our circuit is complete we can generate a spice netlist by navigating to Tools > Generate Netlist.
Image 2: Generating the spice netlist
Some comments on the Netlist options:
The Default format option does not seem to do anything
I have selected Prefix references ‘U’ and ‘IC’ with ‘X’, this is needed for ngspice as it recognizes ‘X’ components as subcircuits. However for the Jack and Power interfaces annotated with J* and P* it would be nice to prefix with X as we will implement these with subcircuits as well.
Once the options are selected click Netlist to save your netlist. This will generate a netlist like the following:
* EESchema Netlist Version 1.1 (Spice format) creation date: Sat 25 Apr 2015 07:04:41 AM JST
* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
XU1 7 6 0 4 1 OPAMP
J1 2 0 0 JACK_IN
J2 7 3 0 JACK_OUT
R2 6 7 50K
R1 2 6 2K
R3 0 3 2K
P1 4 0 1 PWR_IN
Setup Inputs and Outputs for Simulation
In order to simulate the circuit we need to plug in our virtual power supplies, signal generators and oscilloscope probes. To do this I have chosen to use subcircuits to contain each or these test components.
Create a components.cir like the following:
* Components and subcircuits for use in spicedemo.cir
* 4 0 1 PWR_IN
* + g -
.subckt PWR_IN 1 2 3
Vneg 1 2 3.3V
Vpos 2 3 3.3V
* 7 6 0 4 1 OPAMP
* o - + p n
.subckt OPAMP 1 2 3 4 5
* PINOUT ORDER 1 3 6 2 4 5
* PINOUT ORDER +IN -IN +V -V OUT NSD
Xopamp 3 2 4 5 1 NSD LMV981
* s x g
.subckt JACK_IN 1 2 3
*** Simulate mic input A-note
Vmic 3 1 ac SIN(0 0.02 440)
* s x g
.subckt JACK_OUT 1 2 3
Rwire 1 2 10ohm
PWR_IN : Connecting Power
This first subcircuit is the PWR_IN connector in our kicad circuit. This is a 3pin connector with a positive rail, negative rail and ground. Here we use two DC power supplies to generate the positive and negative rails. Be sure to double check pin numbers with your generated netlist.
OPAMP : The IC
Next we have the OPAMP subcircuit. For this we just provide a wrapper for the component included with .INCLUDE LMV981.MOD. This spice model from Texas Instruments and was selected as it provides a 6 pin low power solution. Many vendors provide models like this which can be used.
Image 3: Here we can see how to download spice models from Texas Instruments
JACK_IN : Simulating Microphone Input
The JACK_IN and JACK_OUT interfaces are typical mono audo jack interface with 3 pins (called jack 2-pole). The 3 pins are ‘signal’ (tip), ‘ground’ (sleeve) and ‘normally closed (NC)’. When the jack has nothing plugged into it the ‘signal’ and ‘normally closed’ pins will be shorted. When the jack has something plugged in (like a microphone) then the ‘signal’ and ‘ground’ pins will be connected to the microphone and ‘normally closed’ is disconnected. The reason for this is to protect from having floating inputs or outputs or use for jack plug-in detection.
For JACK_IN we simulate a microphone plugged in by providing a 440hz (a-note) sine wave of 20mV, a typical microphone signal.
JACK_OUT : Simulating a Load
For JACK_OUT we use the dummy load resistor R3 to provide some load to the op amp output. To wire together ‘signal’ and ‘unplugged’ pins we just add a dummy 10ohm resistor. It could have been 0 or 1 ohm, but I just set it to 10.
Update the Generated Netlist
Next, we need to go back and modify the generated netlist slightly to include the components.cir and perform the analysis we wish to do. Also, because we are using subcircuits we add X’s to the J and P components.
Note: Instead of manually adding .include and analysis lines we could add -PSPICE and +PSPICE text blocks anywhere to our kicad schematic and it will include the text before and after the netlist respectively.
Next we can run the TRAN analsysis (oscilloscope mode), to make sure it works. Here we can see that the input signal is amplified from 20mV to 500mV resulting in our expected 25 times gain. The result is also inverted as we are using an inverting amp configuration.
Did you ever get stuck figuring out how to run spice? These essential spice tips will get you on your way.
Recently I have been searching for good linux tools to simulate circuits. Spice is widely known in circuit simulation. This short guide should help you get started; including how to perform graphical plotting with nutmeg. All the below demos are using ngspice and ngnutmeg. In this post I assume you know the basics of writing or generating spice netlists.
We will cover the basics of:
Analysis with OP and TRAN
Controlling spice output
Running ngspice and ngnutmeg
When analyzing a circuit we need to use spice analysis commands. These are usually placed at the end of your netlist.
The first and most simple analysis command you should know is the OP command. It provides the dc operating point voltage dump of all nodes with capacitors fully charged (no current) and inductors fully inducting (shorted).
* OP analysis of Voltage divider
V1 2 0 DC 10V
R1 2 1 50K
R2 1 0 20K
When running we can see that the voltage and current of each node is displayed.
$ ngspice -b op.cir
No. of Data Rows : 1
The next analysis command to know is the TRAN command.
TRAN will run the circuit for a fixed time and take interval measurements. The below .tran 0.1m 5m will measure for 5 milliseconds and output every 0.1 milliseconds. It should print 50 readings. You should choose your measurements based on the frequency of the input source to allow you to see the full wave,
.tran STEP END <START> <MAX>
STEP - is the time interval of how often a measurement is taken
END - is the time when spice will end measurement
START - (default 0) is the time when spice will start measurement
MAX - is used to define a STEP smaller than STEP (yeah confusing)
Note: spice manuals mention the step time of TRAN is not always used by spice. If END-START/50 is less than STEP spice will set step to the smaller value. I haven’t seen this affect my simulations yet.
Lately I have been working on some projects
using verilog. My main development environment has been Altera Quartus II which
works fine. However, when compiling in quartus we don’t always need to go through
all of the sythesis and timing steps, instead one may just need to verify their
source code is compilable.
The vlog compiler included with ModelSim
can be used to quickly compile your HDL.
Today I got my DE0-Nano
FPGA development board. The first thing I wanted to do
was get the linux connectivity setup; so I plugged it in. The device was
recognized as character devide by linux right away.
Next, I checked Altera to see if anything special was needed for getting
USB-Blaster setup in linux. They recommend some
udev example rules
to make the device file world writable, I guess that is ok. I dropped the
udev rules into /etc/udev/rules.d/51-usbblaster.rules and unplugged
then replugged the device but nothing happened.
I havent setup udev rules for a while, so right away I wasn’t able to spot the
problem. I was able to test the rules using udevadm as below.
It complained that BUS and SYSFS matchers were not valid. They were
removed in 2011 according to the udev changelog.
Using udevadm we are also able to see the proper attributes that we should
be matching. Below is what I have come up with to properly setup USB-Blaster
in linux. I am using Fedora 18.
My USB-Blaster udev Rules
Note, since my device is a 6001 I setup a symlink which will make it easily
accessable at /dev/usbblaster1.