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Lately I have been working on some projects using verilog. My main development environment has been Altera Quartus II which works fine. However, when compiling in quartus we don’t always need to go through all of the sythesis and timing steps, instead one may just need to verify their source code is compilable.

The vlog compiler included with ModelSim can be used to quickly compile your HDL.

 # Add module sim onto your path
 $ PATH=$PATH:/usr/share/altera/14.0/modelsim_ase/bin

 # Create a library directory used by 'vlog', by default it looks for 
 # the 'work' library
 $ vlib work

 # Perform the verilog compile
 $ vlog dram_controller.v

 Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013
 -- Compiling module dram_controller

 Top level modules:
    dram_controller

You can find more details on using ModelSim’s command line utilties at the ncsu modelsim tutorial.